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The presented results are obtained from your reports generated from the Xilinx ISE 13.1 instrument suite when the style is targeted to a Spartan-6 gadget. The whole HGW architecture pipeline directly fits simply in to the gadget because of the use of distributed ram sources. Note that the three logic memory modules used in the style are mapped to LUTs inside the FPGA thorough gadget. Only 96 6-input LUTs are necessary to support any kernel size up to 255, which is, a 256 �� eight single-port distributed ram. The maximum clock frequency reported from the tool is 250MHz to get a single HGW module with less than one % of utilization of your target gadget. So, possibly a big variety of HGW modules may be employed without having a substantial maximize of resource utilization or velocity degradation.
The hardware resource utilization for any single HGW is similar to the proposed in  in which 700 slices and 3 Block Rams of 18Kbits were expected. On the other hand, recall that authors used an FPGA engineering counting on 4-input LUTs and in this function, the utilised target gadget natively supports 6-input LUTs; consequently, a a lot more compact implementation is anticipated. However, the use of distributed synchronous ram will allow to replicate the HGW module so as to boost effectiveness. A post-place-and-route simulation model was utilised to estimate the energy consumption of the proposed architecture employing the Xilinx XPower device. The complete power consumption of the 4-HGW design and style is 0.22W, dynamic (0.18W) plus quiescent (0.04W) electrical power.Table 1Summary in the hardware resource utilization for the proposed architecture targeted to a Xilinx Spartan-6 LX45 device for distinct variety of cases in the HGW module.
4.2. Overall performance EvaluationIn buy to get a baseline for comparison, a straightforward implementation for min/max filtering was carried out in C programming language. Also, the Urbach-Wilkinson algorithm  is utilized forPIK-3 comparison functions by using the source code offered by authors. Figure 7 demonstrates the computation times for these techniques over 2160 �� 1440 gray-scale images. The implementations have been carried out on the MacBook Professional with an Intel Core i7 two.66GHz processor and 4GB key memory in ANSI C devoid of multithreading and compiled using gcc with O3 optimization flag set. The computation time for the straightforward implementation grows prohibitively large, not currently being ideal for real-time functionality.
Figure 7 Processing time for the running max/min filters on an 2160 �� 1440 input image with different kernel sizes for a simple implementation and also the Urbach-Wilkinson algorithm. Figure eight shows the close to consistent processing time, about 25 milliseconds, necessary to the architecture to filter a 2160 �� 1440 input image for diverse kernel sizes. Recall that the architecture have to operate twice over the input image considering the fact that it uses kernel decomposition.